This invention relates to a semiconductor device and, in particular, an SOI (Silicon on Insulator) type semiconductor device.
Where a semiconductor device, such as a bipolar IC, is to be manufactured, it is the common practice to initially prepare a semiconductor substrate of one conductivity type. The surface area of the substrate is divided into a number of minute element areas, for example, by field insulation layers. Circuit elements, such as bipolar transistors, are formed in the element areas. In order to obtain bipolar transistors having excellent performances, it is important to decrease the resistivity of the element regions acting as the base, collector and emitter of the transistors and to electrically and sufficiently isolate the element areas of one transistor from that of another transistor.
For a decrease in the resistivity of the element regions, the so-called "embedding" technique is known in which the diffusion regions of a high impurity concentration are formed in the surface area of a substrate and an epitaxial growth layer is formed on the diffusion regions and the substrate. The element regions of circuit elements, e.g., bipolar transistors, are formed in the epitaxial growth layer and in contact with the diffusion regions. For the element isolation, the so-called "pn junction" technique is known in which a diffusion layer is provided to form a pn junction between adjacent element areas. These element areas are electrically insulated by means of reverse biasing the pn junction.
However, the above-mentioned "embedding" technique and "pn junction" technique have the following drawbacks. First, the "embedding" technique requires a greater number of manufacturing steps, as well as a greater deal of time, in embedding the diffusion regions of a high impurity concentration within a semiconductor body. Furthermore, a countermeasure must be taken to prevent an upward diffusion of an impurity from the embedded layer and thus a corresponding increase of its occupation area during the formation of an epitaxial growth layer. In the "pn junction" technique, on the other hand, more manufacturing steps and more time are needed in the formation of a diffusion layer for a pn junction. The use of this technique increases a parasitic capacitance in place of electrically isolating the element areas from each other. Furthermore, the "pn junction" technique is not suitable for the manufacture of ICs for high frequency, because the increase of the parasitic capacitance entails a degradation in the high frequency characteristic of the circuit elements.
In a high-integrated semiconductor device, in particular, a bipolar IC, not only the above-mentioned technique but also, for example, an SOS (Silicon on Sapphire) technique has already been known in the art. The SOS technique involves the use of expensive sapphire. Therefore, the manufacturing cost is hard to reduce by high integration.
The SOI (Silicon on Insulator) technique is now at the developmental stage. In this technique, an oxide film is formed on the surface of a semiconductor substrate and an epitaxial growth layer is formed on the oxide film. However, such a structure is not reduced in practice in the fabrication of an integrated circuit with a high integration density.